The present invention relates in general to integrated circuits, and in particular to a number of circuit techniques that protect output transistors from signals experiencing overshoot and undershoot at the output node and bias voltage generators for such circuits.
In the field of semiconductor technology, there is continued research and development efforts focused on building next generation devices that are smaller and faster. Reduction in power consumption is another objective of the circuit designers as the demand for battery operated portable electronic devices continues to grow. To reduce power consumption, circuits are being designed with ever decreasing power supply voltages. The current state of the art is pushing the level of the power supply voltages to as low as 1.9 volts for microprocessor circuits and the like. On the other hand, to make integrated circuits faster, field effect transistors are being manufactured with thinner gate oxide layers which limit the voltage swing across the transistor. The maximum tolerable voltage across a transistor in a low voltage circuit that is made up of fast, thin oxide transistors, may in fact be limited to the power supply voltage level. Thus, such a circuit operating with, for example, 1.9 volt supply voltage, must ensure that none of the transistors are subject to voltages greater than 1.9 volts. While protection against voltage stress conditions for transistors that are internal to an integrated circuit may not be an issue, transistors in the input/output (I/O) circuitry may well be exposed to larger than expected external signals.
A typical CMOS output buffer is made up of a CMOS inverter having a p-channel pull-up transistor connected to an n-channel pull-down transistor. The common drain terminal of the two devices connects to an external terminal that is typically connected to other circuitry via a transmission line. Mismatches in the impedance of drivers and transmission lines give rise to signal overshoot and undershoot conditions on the transmission lines. Thus, the output transistors may experience voltages greater than that allowed by the process causing reliability problems and damage to output transistor gate oxide. A common prior art technique has been to insert cascode devices in series with the I/O transistors such that any one transistor experiences less of the overshoot or undershoot. However, such cascode devices limit the speed of the output driver and, at lower power supply voltages, severely limit the output swing of the circuit.
There is therefore a need for an output buffer circuit that can be implemented with low voltage transistors and can that safely withstand overshoot or undershoot conditions.